This invention relates to voltage controlled crystal oscillators, and in particular, to cost-effective circuit configurations for relatively high frequency voltage controlled crystal oscillators.
High capacity data networks rely on signal repeaters and sensitive receivers for low-error data transmission. To decode and/or cleanly retransmit a serial data signal, such network components include components for creating a data timing signal having the same phase and frequency as the data signal. This step of creating a timing signal has been labeled xe2x80x9cclock recovery.xe2x80x9d
Data clock recovery requires a relatively high purity reference signal to serve as a starting point for matching the serial data signal clock rate and also circuitry for frequency adjustment. The type, cost and quality of the technology employed to generate the high purity reference signal varies according to the class of data network applications. For fixed large-scale installations, an xe2x80x9catomicxe2x80x9d clock may serve as the ultimate source of the reference signal. For remote or movable systems, components including specially configured quartz resonators have been used. As communication network technology progresses towards providing higher bandwidth interconnections to local area networks and computer workstations, the need has grown for smaller and cheaper clock recovery technology solutions.
For higher frequency applications now in demand, e.g., above 500 MHz, more conventional resonator technologies such as standard AT-cut crystals have not been fully successful. The recognized upper limit for fundamental-mode, straight blank AT-cut crystals is about 70 MHz. Hence, some type of frequency multiplication must be employed to generate the required higher frequency reference signal. With frequency multiplication comes increased circuit sensitivities for phase noise, jitter, non-linearities and long-term stability.
Available alternatives to standard quartz/crystal resonators include the use of surface acoustic wave (SAW) resonators and special crystal blank configurations such as inverted mesa. These alternatives involve more complex manufacturing steps and therefore higher cost.
The focus on cost cutting for data signal clock recovery components is reflected in U.S. Pat. No. 5,987,085 to Anderson. The Anderson patent illustrates a clock recovery circuit developed in an effort to eliminate the crystal-based reference clock requirement. Anderson failed to identify the target frequencies or present operating data, however.
Thus, there continues to be a need for a cost-effective voltage controlled crystal oscillator suitable for data signal clock recovery applications. Specifically, it would be desirable to provide a high frequency voltage controlled oscillator utilizing conventional crystal resonators.
A controllable oscillator suitable for use in digital signal clock synchronization is provided. The oscillator includes a crystal oscillator circuit for generating a driving signal, a phase detector circuit, a low pass loop filter, a voltage controlled oscillator (VCO) circuit, a frequency divider circuit and a sinewave-to-logic level translator circuit.
The crystal oscillator circuit generates a driving signal and has a voltage-variable control input for adjusting the frequency of the driving signal. The crystal oscillator circuit further includes a voltage variable capacitance element, such as a discrete varactor responsive to the control input, an AT-cut quartz resonator operably linked to the varactor, and a gain stage for energizing the discrete varactor.
The phase detector subcircuit is adapted to generate a phase offset signal. The loop filter operates on the phase offset signal to produce a control voltage, which is received by the voltage controlled oscillator (VCO) subcircuit. The voltage controlled oscillator (VCO) circuit is operably linked to the loop filter and responsive to the control voltage for generating an analog controlled-frequency signal.
The frequency divider circuit has a preselectable divider ratio and is operably linked between the voltage controlled-frequency oscillator circuit and the phase detector circuit. The frequency divider generates a reduced frequency feedback signal in response to the controlled-frequency signal. The phase detector circuit is responsive to the feedback signal and the driving signal such that the phase offset signal varies according to a phase difference between the feedback signal and the driving signal.
The oscillator also includes the sinewave-to-logic level translator subcircuit which is operably linked to the voltage controlled oscillator (VCO) for generating a digital (or logic level) output signal having substantially the same frequency as the controlled-frequency signal.
In a preferred embodiment, the AT-cut quartz resonator is adapted to resonate in fundamental mode at about 19.44 Megahertz, the divider subcircuit has a preselected divider ratio of about 32:1 and the oscillator exhibits an operating frequency within the area defined between the following two equations:
f1output=0.04526(Vcontrol)+621.9430 Megahertz
f2output=0.04526(Vcontrol)+621.9679 Megahertz
for Vcontrol values in the range of about 0.15 volts to about 3.15 volts, where Vcontrol is a DC voltage level of the voltage-variable input.
An alternate embodiment of the present invention is a frequency-adjustable oscillator with reduced temperature dependence. The frequency-adjustable oscillator includes a phase detector circuit for generating a phase offset signal, a loop filter operating on the phase offset signal to produce a VCO control signal, a voltage controlled oscillator circuit operably linked to the filter and responsive to the VCO control signal for generating an analog controlled-frequency signal and a frequency divider circuit operably linked between the voltage controlled-frequency oscillator circuit and the phase detector circuit for generating a reduced frequency feedback signal in response to the controlled-frequency signal.
The phase detector circuit is responsive to the feedback signal and a driving signal such that the phase offset signal varies according to a phase difference between the feedback signal and the driving signal. The driving signal is generated by a quartz resonator operably linked to a resonator gain stage and a variable capacitance circuit. The variable capacitance circuit is linked to a temperature compensation logic, a temperature sensor, and a control input. The temperature compensation logic generates a capacitance adjustment in response to temperature changes to block temperature induced frequency variations. Via the variable capacitance circuit, the control input effects changes to the resonator capacitive load to allow precise external control of the driving frequency.
There are other advantages and features of this invention which will be more readily apparent from the following detailed description of the preferred embodiment of the invention, the drawings, and the appended claims.